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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos 4-/8-channel high performance analog multiplexers adg408/adg409 features 44 v supply maximum ratings v ss to v dd analog signal range low on resistance (100 v max) low power (i supply < 75 m a) fast switching break-before-make switching action plug-in replacement for dg408/dg409 applications audio and video routing automatic test equipment data acquisition systems battery powered systems sample and hold systems communication systems general description the adg408 and adg409 are monolithic cmos analog multiplexers comprising eight single channels and four differen- tial channels respectively. the adg408 switches one of eight inputs to a common output as determined by the 3-bit binary address lines a0, a1 and a2. the adg409 switches one of four differential inputs to a common differential output as deter- mined by the 2-bit binary address lines a0 and a1. an en input on both devices is used to enable or disable the device. when disabled, all channels are switched off. the adg408/adg409 are designed on an enhanced lc 2 mos process which provides low power dissipation yet gives high switching speed and low on resistance. each channel conducts equally well in both directions when on and has an input signal range that extends to the supplies. in the off condition, signal levels up to the supplies are blocked. all channels exhibit break- before-make switching action, preventing momentary shorting when switching channels. inherent in the design is low charge injection for minimum transients when switching the digital inputs. the adg408/adg409 are improved replacements for the dg408/dg409 analog multiplexers. product highlights 1. extended signal range the adg408/adg409 are fabricated on an enhanced lc 2 mos process giving an increased signal range that extends to the supply rails. 2. low power dissipation 3 low r on 4. single supply operation for applications where the analog signal is unipolar, the adg408/adg409 can be operated from a single rail power supply. the parts are fully specified with a single +12 v power supply and will remain functional with single supplies as low as +5 v. functional block diagrams adg408 1 of 8 decoder s1 s8 d a0 a1 a2 en adg409 1 of 4 decoder s1a s4b da a0 a1 en db s4a s1b one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1998
adg408/adg409Cspecifications dual supply 1 b version t version C40 8 c to C55 8 c to parameter +25 8 c +85 8 c +25 8 c +125 8 c units test conditions/comments analog switch analog signal range v ss to v dd v ss to v dd v r on 40 40 w typ v d = 10 v, i s = C10 ma 100 125 100 125 w max d r on 15 15 w max v d = +10 v, C10 v leakage currents source off leakage i s (off) 0.5 50 0.5 50 na max v d = 10 v, v s = 7 10 v; test circuit 2 drain off leakage i d (off) v d = 10 v; v s = 7 10 v; adg408 1 100 1 100 na max test circuit 3 adg409 1 50 1 50 na max channel on leakage i d , i s (on) v s = v d = 10 v; adg408 1 100 1 100 na max test circuit 4 adg409 1 50 1 50 na max digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 10 10 m a max v in = 0 or v dd c in , digital input capacitance 8 8 pf typ f = 1 mhz dynamic characteristics 2 t transition 120 120 ns typ r l = 300 w , c l = 35 pf; 250 250 ns max v s1 = 10 v, v ss = 7 10 v; test circuit 5 t open 10 10 10 10 ns min r l = 300 w , c l = 35 pf; v s = +5 v; test circuit 6 t on (en) 85 125 85 125 ns typ r l = 300 w , c l = 35 pf; 150 225 150 225 ns max v s = +5 v; test circuit 7 t off (en) 65 65 ns typ r l = 300 w , c l = 35 pf; 150 150 ns max v s = +5 v; test circuit 7 charge injection 20 20 pc typ v s = 0 v, r s = 0 w , c l = 10 nf; test circuit 8 off isolation C75 C75 db typ r l = 1 k w , f = 100 khz; v en = 0 v; test circuit 9 channel-to-channel crosstalk 85 85 db typ r l = 1 k w , f = 100 khz; test circuit 10 c s (off) 11 11 pf typ f = 1 mhz c d (off) f = 1 mhz adg408 40 40 pf typ adg409 20 20 pf typ c d , c s (on) f = 1 mhz adg408 54 54 pf typ adg409 34 34 pf typ power requirements i dd 11 m a typ v in = 0 v, v en = 0 v 55 m a max i ss 11 m a typ 55 m a max i dd 100 100 m a typ v in = 0 v, v en = 2.4 v 200 500 200 500 m a max notes 1 temperature ranges are as follows: b version: C40 c to +85 c; t version: C55 c to +125 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. rev. a C2C (v dd = +15 v, v ss = C15 v, gnd = 0 v, unless otherwise noted)
C3C rev. a adg408/adg409 single supply 1 b version t version C40 8 c to C55 8 c to parameter +25 8 c +85 8 c +25 8 c +125 8 c units test conditions/comments analog switch analog signal range 0 to v dd 0 to v dd v r on 90 90 w typ v d = +3 v, +10 v, i s = C1 ma leakage currents source off leakage i s (off) 0.5 50 0.5 50 na max v d =8 v/0 v, v s = 0 v/8 v; test circuit 2 drain off leakage i d (off) v d =8 v/0 v, v s = 0 v/8 v; adg408 1 100 1 100 na max test circuit 3 adg409 1 50 1 50 na max channel on leakage i d , i s (on) v s = v d = 8 v/0 v; adg408 1 100 1 100 na max test circuit 4 adg409 1 50 1 50 na max digital inputs input high voltage, v inh 2.4 2.4 v min input low voltage, v inl 0.8 0.8 v max input current i inl or i inh 10 10 m a max v in = 0 or v dd c in , digital input capacitance 8 8 pf typ f = 1 mhz dynamic characteristics 2 t transition 130 130 ns typ r l = 300 w , c l = 35 pf; v s1 = 8 v/0 v, v s8 = 0 v/8 v; test circuit 5 t open 10 10 ns typ r l = 300 w , c l = 35 pf; v s = +5 v; test circuit 6 t on (en) 140 140 ns typ r l = 300 w , c l = 35 pf; v s = +5 v; test circuit 7 t off (en) 60 60 ns typ r l = 300 w , c l = 35 pf; v s = +5 v; test circuit 7 charge injection 5 5 pc typ v s = 0 v, r s = 0 w , c l = 10 nf; test circuit 8 off isolation C75 C75 db typ r l = 1 k w , f = 100 khz; v en = 0 v; test circuit 9 channel-to-channel crosstalk 85 85 db typ r l = 1 k w , f = 100 khz; test circuit 10 c s (off) 11 11 pf typ f = 1 mhz c d (off) f = 1 mhz adg408 40 40 pf typ adg409 20 20 pf typ c d , c s (on) f = 1 mhz adg408 54 54 pf typ adg409 34 34 pf typ power requirements i dd 11 m a typ v in = 0 v, v en = 0 v 55 m a max i dd 100 100 m a typ v in = 0 v, v en = 2.4 v 200 500 200 500 m a max notes 1 temperature ranges are as follows: b version: C40 c to +85 c; t version: C55 c to +125 c. 2 guaranteed by design, not subject to production test. specifications subject to change without notice. (v dd = +12 v, v ss = 0 v, gnd = 0 v, unless otherwise noted)
adg408/adg409 rev. a C4C absolute maximum ratings 1 (t a = +25 c unless otherwise noted) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +25 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C25 v analog, digital inputs 2 . . . . . v ss C2 v to v dd +2 v or 20 ma, whichever occurs first continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 20 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle max) . . . . . . . . . . . 40 ma operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . C40 c to +85 c extended (t version) . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150 c cerdip package, power dissipation . . . . . . . . . . . . . . . 900 mw q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 76 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . +300 c plastic package, power dissipation . . . . . . . . . . . . . . . 470 mw q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 117 c/w lead temperature, soldering (10 sec) . . . . . . . . . . . +260 c tssop package, power dissipation . . . . . . . . . . . . . . 450 mw q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . 155 c/w q jc , thermal impedance . . . . . . . . . . . . . . . . . . . . . 50 c/w soic package, power dissipation . . . . . . . . . . . . . . . . 600 mw q ja , thermal impedance . . . . . . . . . . . . . . . . . . . . . 77 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at a, en, s or d will be clamped by internal diodes. current should be limited to the maximum ratings given. ordering information model 1 temperature range package option 2 ADG408BN C40 c to +85 c n-16 adg408br C40 c to +85 c r-16a adg408bru C40 c to +85 c ru-16 adg408tq C55 c to +125 c q-16 adg409bn C40 c to +85 c n-16 adg409br C40 c to +85 c r-16a adg409tq C55 c to +125 c q-16 notes 1 to order mil-std-883, class b processed parts, add /883b to t grade part numbers. 2 n = plastic dip; q = cerdip; r = 0.15" small outline ic (soic); ru = think shrink small outline package (tssop). caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adg408/adg409 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
adg408/adg409 rev. a C5C terminology v dd most positive power supply potential. v ss most negative power supply potential in dual supplies. in single supply applications, it may be connected to ground. gnd ground (0 v) reference. r on ohmic resistance between d and s. d r on difference between the r on of any two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminals d, s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to an other. t open off time measured between the 80% point of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off channel. charge a measure of the glitch impulse transferred injection from the digital input to the analog output during switching. i dd positive supply current. i ss negative supply current. pin configurations (dip/soic/tssop) top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 a0 en v ss s1 s2 s3 s4 d a1 a2 gnd v dd s5 s6 s7 s8 adg408 top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 a0 en v ss s1a s2a s3a s4a da a1 gnd v dd s1b s2b s3b s4b db adg409 adg408 truth table on a2 a1 a0 en switch x x x 0 none 00011 00112 01013 01114 10015 10116 11017 11118 adg409 truth table on switch al a0 en pair x x 0 none 0011 0112 1013 1114
adg408/adg409 rev. a C6C typical performance characteristics v d (v s ) C volts 120 20 C15 15 C10 r on C v C5 0 5 10 80 40 100 60 v dd = +10v v ss = C10v v dd = +5v v ss = C5v v dd = +12v v ss = C12v v dd = +15v v ss = C15v t a = +25 8 c figure 1. r on as a function of v d (v s ): dual supply voltage v d (v s ) C volts 100 30 C15 15 C10 r on C v C5 0 5 10 80 70 50 40 60 90 +125 8 c +85 8 c +25 8 c v dd = +15v v ss = C15v figure 2. r on as a function of v d (v s ) for different temperatures v d (v s ) C volts 0.2 C0.2 leakage current C na 0 C0.1 0.1 C15 15 C10 C5 0 5 10 t a = +25 8 c v dd = +15v v ss = C15v i s (off) i d (on) i d (off) figure 3. leakage currents as a function of v d (v s ) v d (v s ) C volts 180 40 015 3 r on C v 6912 140 120 80 60 160 100 t a = +25 8 c v dd = +5v v ss = 0v v dd = +12v v ss = 0v v dd = +15v v ss = 0v v dd = +10v v ss = 0v figure 4. r on as a function of v d (v s ): single supply voltage v d (v s ) C volts 130 60 012 2 r on C v 46810 100 80 70 90 120 v dd = +12v v ss = 0v +125 8 c +85 8 c +25 8 c 110 figure 5. r on as a function of v d (v s ) for different temperatures v d (v s ) C volts 0.04 C0.06 012 2 leakage current C na 46810 0 C0.04 0.02 C0.02 t a = +25 8 c v dd = +12v v ss = 0v i s (off) i d (on) i d (off) figure 6. leakage currents as a function of v d (v s )
adg408/adg409 rev. a C7C v in C volts 120 20 115 3 t C ns 5791113 60 40 100 80 v dd = +15v v ss = C15v t transition t on (en) t off (en) figure 7. switching time vs. v in (bipolar supply) v supply C volts 400 0 515 7 t C ns 91113 200 100 300 v in = +5v t transition t on (en) t off (en) figure 8. switching time vs. single supply frequency C hz 10 4 10 3 10 2 i dd C m a 10m 10 100 1k 10k 100k 1m v dd = +15v v ss = C15v en = 2.4v en = 0v figure 9. pos itive supply current vs. switching frequency v in C volts 140 40 113 3 t C ns 57911 100 60 120 80 v dd = +12v v ss = 0v t transition t on (en) t off (en) figure 10. switching time vs. v in (single supply) v supply C volts 300 0 6 5 6 15 6 7 t C ns 6 9 6 11 6 13 200 100 v in = +5v t transition t on (en) t off (en) figure 11. switching time vs. bipolar supply en = 0v frequency C hz 10 4 10 3 10 C1 10m 1m 10 i ss C m a 100 1k 10k 100k 10 2 10 1 10 0 v dd = +15v v ss = C15v en = 2.4v figure 12. negative supply current vs. switching frequency
adg408/adg409 rev. a C8C frequency C hz 110 70 1k 1m 10k off isolation C db 100k 90 80 100 v dd = +15v v ss = C15v figure 13. off isolation vs. frequency v dd = +15v v ss = C15v frequency C hz 110 70 1k 1m 10k crosstalk C db 100k 90 80 100 60 figure 14. crosstalk vs. frequency test circuits i ds v1 sd v s r on = v1/i ds test circuit 1. on resistance s1 d s2 s8 a en gnd v dd v ss v dd v ss +0.8v v d v s i s (off) test circuit 2. i s (off) s1 d s2 s8 a en gnd v dd v ss v dd v ss +0.8v v d v s i d (off) test circuit 3. i d (off) s1 d s8 a en gnd v dd v ss v dd v ss 2.4v v d v s i d (on) test circuit 4. i d (on)
adg408/adg409 rev. a C9C v dd v ss v dd v ss v s1 v s8 output adg408* a0 a1 a2 50 v v in 2.4v en gnd s1 s2 thru s7 s8 d 300 v 35pf *similar connection for adg409 3v 0v enable drive (v in ) t transition t transition output 50% 50% 90% 90% t r < 20ns t f < 20ns test circuit 5. switching time of multiplexer, t transltlon v dd v ss v dd v ss v s output adg408* a0 a1 a2 50 v v in 2.4v en gnd s1 s2 thru s7 s8 d 300 v 35pf *similar connection for adg409 3v 0v address drive (v in ) output 80% 80% t open test circuit 6. break-before-make delay, t open v dd v ss v dd v ss v s output adg408* a0 a1 a2 en gnd s1 s2 thru s8 d 300 v 35pf *similar connection for adg409 50 v v in 3v 0v enable drive (v in ) output 50% 50% t on (en) t off (en) 0.9v o 0.9v o test circuit 7. enable delay, t on (en), t off (en)
adg408/adg409 rev. a C10C v dd v ss v dd v ss adg408* a0 a1 a2 en gnd d *similar connection for adg409 v in v out s c l 10nf r s v s d v out 3v v in v out q inj = c l 3 d v out test circuit 8. charge injection v dd v ss v dd v ss adg408 a0 a1 a2 en gnd d v out s1 v s s8 0v 1k v off isolation = 20 log v out /v in test circuit 9. off isolation v dd v ss v dd v ss adg408 a0 a1 a2 en gnd d s1 v s s8 v out 1k v crosstalk = 20 log v out /v in s2 1k v 2.4v test circuit 10. channel-to-channel crosstalk
adg408/adg409 rev. a C11C outline dimensions dimensions shown in inches and (mm). plastic dip (n-16) 16 18 9 pin 1 0.87 (22.1) max 0.25 (6.35) 0.31 (7.87) seating plane 0.100 (2.54) bsc 0.18 (4.57) 0.035 (0.89) 0.125 (3.18) min 0.018 (0.46) 0.033 (0.84) 0.18 (4.57) max 0.3 (7.62) 0.011 (0.28) cerdip (q-16) 16 1 8 9 0.310 (7.87) 0.220 (5.59) pin 1 0.005 (0.13) min 0.080 (2.03) max seating plane 0.022 (0.558) 0.014 (0.356) 0.200 (5.08) max 0.840 (21.34) max 0.150 (3.81) min 0.070 (1.78) 0.030 (0.76) 0.200 (5.08) 0.125 (3.18) 0.100 (2.54) bsc 0.060 (1.52) 0.015 (0.38) 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) so (narrow body) (r-16a) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 thin shrink small outline package (tssop) (ru-16) 16 9 8 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 c1824aC0C4/98 printed in u.s.a.

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